The latest episode from ‘Mum, I’m Building a CPU’ is online (below). In it we talk about the program counter and a few other goodies!
Since last week, we have added numerous arithmetic unit boards to our CPU as well as found an entire bus that was positioned wrongly! Andrei has been working on connecting his full ripple-adder to the flip-flops, and Charlie and I have been working on various other boards, including the program counter and a shift/rotate functional unit (more about this one next week).
The program counter has an interesting story behind it. Initially, we were just looking at getting a register that would be incremented when clocked. Then we realised it needed to be programmable to support our jump instructions (for moving between instructions and into subroutines). We all spent a lot of time trying to find an IC that did this, and I thought I had found a CMOS IC that looked hopeful, but it was complex to program. We were doing all this because we didn’t want to manually add ‘1’ to a 8 bit register, worried it would lead to constructing another 8 bit full adder (see Episode 2 for a discussion of this).
Realising that this appeared to be the only way, Charlie and I sat down on Saturday morning to see if we could minimise the logic required to cut down on the wiring and IC’s. And low and behold, we did (albeit via a rather round about way)! After completing an SOP representation and a KMAP, we put them into ‘Simple Solver‘ which said if we were tying one input to Vcc (a logical ‘1’) all we needed was an XOR and an AND. And if you think about that, it makes perfect sense.
- Take any binary number and add ‘1’ to it – this flips the least significant bit.
- Then, for each next significant bit, you are just adding two things together – A (the bit) and Cin (the carry in).
- So, put both A and Cin though an AND gate. This represents Cout (the carry out) – if you get a 1 you need to send that to the carry in on the next significant bit when performing that sum. If not, the carry out is set to 0.
- Then, put A and Cin into an XOR gate. If both are 0, the result will be 0, if exactly one is 1, the result will be 1 (0+1 = 1) and if both are 1, the result will be 0 (and this makes sense, because 1+1 = 2, and this is higher than can be represented in one binary bit, so you need to send a carry to the next significant bit’s sum, done via the above AND gate).
We really shouldn’t have needed software help for that! Anyway, I hope you enjoy the quick video update below.
Lots has changed with our CPU project over the last two weeks. Firstly, and most importantly, Andrei has finished our 8-bit ripple adder. Charlie and I have also worked on the negator board for subtraction (more here about that). All that in the next episode though. This week, we take you through the architecture of the overall project (in block diagram form).
And here is the higher-resolution cleaner version of our architecture diagram:
Andrei’s 8-bit full (ripple) adder is now complete (see below), so Charlie and I have been able to look at subtraction.
To support subtraction, Charlie and I have build a negation board. When a data-value is sent to the addition board, one copy of it will go through a series of not gates whilst the other does not. Both then go through a multiplexer (74245) which selects which one to send on to the adder board. We did realise on Saturday however that the whole thing can be re-built with eight XOR gates, where we can choose whether to invert each bit by putting either a 0 or 1 on one of the inputs.
One thing that has taken some thinking about with this board is how we accurately perform subtractions – the problem lays with Binary. Lets take a simple example (most-significant-bit is a sign bit, b = binary):
00010011b = 19
now let’s swap the 0’s and 1’s
11101100b = 236
236-(2^8) = -20 (since we have 8 bits)
So, you see our result is one less than the desired one. The solution that we are working on is a negation of the carry flag before it is sent to the adder. Once I’ve looked more at this I’ll update this post with a Truth-Table.